Digital data may flow through an IC via numerous logic paths. Such paths may include sequential logic—clocks, one-shots, and memory circuits such as flip-flops. In some ICs, the overall throughput of data may be limited by the data-to-output lag (tDQ) of a memory circuit, which is a function of the data-setup time (tS) and the clock-to-output lag (tCQ). It may be desirable, therefore, to reduce both the tS and the tCQ of memory circuits that limit data throughput.
Furthermore, sequential logic operating at very high clock speeds may be prone to the effects of clock skew, clock jitter, and within-die delay variations, which can cause logic errors. One way to avoid such errors is to reduce the clock speed, which also reduces data throughput. A better alternative may be to implement time borrowing. Time borrowing is useful for absorbing clock skew and clock jitter and for averaging out within-die delay variations. This approach can extend the useful range of clock speed in an IC. Time-borrowing concepts may not be applicable, however, to every type of memory circuit.
Accordingly, the disclosure herein provides a novel class of memory circuit which exhibits attractively short tS and tCQ characteristics and is amenable to time borrowing.